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Tiempo Secure’s new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests

July 2023 by Marc Jacob

Tiempo Secure, leveraged its long-standing know-how in the field of security IP for microelectronics, to deploy its TESIC design with a RISC-V core. This new IP is critical for any Secure Element or Secure Enclave - an essential technology for building a certified secure component, to guarantee security for IoT wired or wireless communications, iSIM, root of trust secure designs, and HSM.

TESIC is Tiempo Secure’s security architecture, which now includes a RISC-V MCU, memories (ROM, RAM, Cache, Crypto-RAM, and MRAM non-volatile memory), random number generators, security sensors, and asynchronous crypto-accelerators, to support various types of symmetrical and asymmetrical cryptographic algorithms. Based on this IP, Tiempo Secure has designed a RISC-V test chip that was successfully evaluated by SERMA. To conduct the security evaluation, the Tiempo Secure design was manufactured in the form of a test chip, using Global Foundry GF22 FDX technology with MRAM. This also enabled Tiempo to validate the compatibility of TESIC with GF22 technology.

During the series of tests which were carried out over 5 months, particular emphasis was placed on side channel attacks and fault attacks. To reach the highest security assessment level, the die was packaged without resin, therefore making it more vulnerable and boosting the potential success rates of attacks. The result of the evaluation was successful, enabling Tiempo to validate both the hardware and software countermeasures implemented in the circuit that had been subjected to the tests.

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