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Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP for 5-Nanometer Process in AI and High-Performance Computing SoCs

January 2021 by Marc Jacob

Synopsys, Inc. and Socionext, Inc. announced their collaboration to expand Socionext’s use of Synopsys’ broad DesignWare® IP to include Synopsys’ HBM2E IP for maximum memory throughput in AI and high-performance computing (HPC) applications. Socionext selected Synopsys’ HBM2E IP, operating at 3.6 Gbps, to meet the stringent capacity, power, and compute performance requirements of its innovative AI engine and accelerator system-on-chip (SoC). The Synopsys IP provides efficient heterogeneous integration with the shortest 2.5D interposer package routes.

With an aggregated bandwidth of 460 gigabytes per second, the DesignWare HBM2E PHY IP delivers the required massive compute performance of SoCs in advanced FinFET processes. The HBM2E IP is part of Synopsys’ comprehensive memory interface IP solution that includes DDR5/4/3/2 and LPDDR5/4/4X/3/2 IP, which have been validated in hundreds of designs and shipped in millions of SoCs.

Availability and Resources
The Synopsys DesignWare HBM2/2E IP in a wide range of processes from 16-nm to 5-nm is available now. For more information, visit the DesignWare HBM2/2E IP and 3DIC Compiler: unified platform for end-to-end multi-die integration in a package web pages.




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