Contactez-nous Suivez-nous sur Twitter En francais English Language

De la Théorie à la pratique

Freely subscribe to our NEWSLETTER

Newsletter FR

Newsletter EN



Mirabilis Design announces an Application-Specific University Program

July 2020 by Marc Jacob

Mirabilis Design announced today an University Program that covers one hundred and fifty applications ranging from designing processors to data center capacity planning. With this program, Mirabilis Design will provide real-life design and exploration experience to University students in Electrical, Electronics, Computer Engineering and Computer Science streams. The cost of setting up a separate Lab for each application area is prohibitive for most Universities. With this approach, Universities can offer applications in semiconductor, automotive, communication, networking, wireless, data center, radars and multimedia to their students for access from college labs and remote desktops.

This Program provides large number of copies of VisualSim Architects, technology standards and pre-built application templates. VisualSim is a graphical modeling and simulation environment that is used by companies worldwide to design and explore the architecture of advanced systems, including hardware, software, networks, semiconductors, and semiconductor IP. Students can develop and innovate emerging topics such as Artificial Intelligence processors, Autonomous Driving Systems, 5G Wireless Networks, Radar systems, software networking and Data Center Cloud. VisualSim has over 500 building blocks that include Arm/x86 processors, GPU, DSP, DMA, AMBA, TileLink, NoC. Ethernet, CAN, PCIe, DRAM DDR5, FPGAs (Xilinx, Intel and Microsemi), data center servers using x86, RTOS and stochastic components.

A unique feature of the University program is the availability of teaching material in the forms of slides, laboratory manuals and technical notes and reference material for new technologies. The laboratory study includes the impact of mutex on real-time code in a ADAS vehicle, RoundRobin priority in an Ethernet Scheduler, Network-on-Chip on a Processor-Memory access, distribution of safety and non-safety RTOS on Hypervisor, multi-server stacks in data center and software partitioning on a multi-core processor. Students can gain hands-on experience with topics covered in the curriculum. The impact can be evaluated on power, timing, throughput, and incorrect configuration.

See previous articles


See next articles